1. Field of the Invention
This invention relates to a nonvolatile semiconductor device that has, for example, floating gates.
2. Description of the Related Art
Most NAND-type nonvolatile semiconductor memories have EEPROM cells, or cell transistors. A group of cell transistors are connected in series, having a common source-drain region. Each cell transistor has a multi-layered gate structure, having a floating gate and a control gate. The control gate is formed on a gate insulating film that is provided on the floating gate. Cell transistors of a group share one floating gate, which serves as a word line. The floating gates of any adjacent cell transistors are spaced apart and electrically isolated. The cell transistors connected in series constitute a NAND cell. The ends of the NAND cell are connected to two selection transistors, respectively. One selection transistor connects one end of the NAND cell to a bit line. The other selection transistor connects the other end of the NAND cell to a source line. Electrons are injected into the floating gate common to the cell transistors by applying a high write potential to the control gates of the cell transistors and connecting the substrate to the ground.
As cell transistors become smaller and smaller, the parasitic capacitance between any adjacent cell transistors increases. So does the parasitic capacitance between the floating gate of each cell transistor and the structure peripheral to the cell transistor. The write voltage to be applied to each cell transistor must be increased to write data at high speed. In order to increase the write voltage, the control gates of the cell transistors must be sufficiently insulated against the write voltage and the word-line drive circuit must be greatly resistant to the write voltage. This makes it difficult to increase the packing density of memory elements and raise the operating speed thereof.
In view of this, it has been proposed that the floating gate and control gate of each cell transistor be changed in structure to lower the write voltage.
For example, a NAND-type EEPROM has been developed, in which the capacitance between the booster plate and the floating gate of each cell transistor is increased. Thus, data can be written into, erased in and read from, this NAND-type EEPROM at a low voltage (See, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-145429).
A nonvolatile memory element has been developed, in which the coupling ratio between the floating gate and the control gate is increased, thus lowering the write voltage. The memory element can therefore be small. (See, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-217318.)
A nonvolatile semiconductor memory having MOSFETs used as cell transistors has been developed. In this memory, each MOSFET has two floating gates provided on the sides of the control gate. These floating gates help to improve the data-writing, -erasing and -reading characteristics of the memory. (See, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-50703.)
So-called AG-AND memory cells have been developed. (See, for example, 10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology, 2002 IEEE, 952-IEDM, 21.6.1.) The AG-AND memory cell has an assistant gate that is located adjacent to the floating gate.
In NAND-type nonvolatile semiconductor memories comprising each comprising cell transistors, each having a floating gate and a control gate laid one above the other, the selection gates have the same structure as the cell transistors. That is, each selection gate comprises a floating gate and a control gate electrically connected to the floating gate. Hence, the selection gates arranged along any word line can be connected together if their control gates are connected to one another.
If each cell transistor has two floating gates that are provided on the sides of the control gate, however, shallow trench isolation (STI) is provided between any two selection gates arranged along a word line. This makes it difficult to connect the selection gates.